This invention relates to a semiconductor memory device having a protect function against illegal copy and a method for accessing the same.
The memory cell array of a semiconductor memory device, for example, a mask ROM (Read Only Memory) is constructed by arranging memory cells which are formed of MOS transistors in a matrix form of rows and columns, connecting the gates of the memory cells on each row to a corresponding one of a plurality of word lines, connecting the drains of the memory cells on each column to a corresponding one of a plurality of bit lines, and connecting the sources thereof to the ground node. As a method for writing data into each memory cell, (a) a diffused layer programming method, (b) an ion-implantation programming method, and (c) a contact programming method are known, and data is written by using a photomask in the course of the manufacturing process by defining "0", "1" of memory information according to whether a MOS transistor is formed or not, whether the MOS transistor is of depletion type or enhancement type, or whether a contact hole is formed or not, for example. Memory data is read out by selecting and charging a bit line, selecting a word line and setting the potential thereof to a high level and determining "0", "1" of memory information according to whether or not the bit line is discharged via a MOS transistor (memory cell) which is connected to the selected bit line and word line.
FIG. 1 is a block diagram showing the schematic construction of the conventional mask ROM described above. In a memory cell array 11, memory cells constructed by MOS transistors are arranged in a matrix form. A row address buffer 12 is supplied with a row address signal and latches the same in response to a /RAS ("/" attached before the symbol indicates an inverted signal, that is, a bar) signal. A column address buffer 13 is supplied with a column address signal and latches the same in response to a /CAS signal. A row decoder 14 selectively drives one of the word lines in the memory cell array 11 by decoding a row address signal output from the row address buffer 12 so as to select one row of the memory cells. A column address counter 15 is controlled by the /CAS signal and a latch output of the column address buffer 13 is set therein. The column address counter 15 sequentially counts up set data to create a column address signal. A column selection gate 16 selectively activates one of the bit lines in the memory cell array 11. A column decoder 17 decodes a column address signal output from the column address counter 15 to control the column selection gate 16 and select one column of the memory cells. A sense amplifier 18 amplifies data read out from a selected one of the memory cells in the memory cell array 11. An output buffer 19 is controlled by an /OE signal and outputs a signal amplified by the sense amplifier 18 via a data bus DB.
With the above construction, if a row address signal is input to the row address buffer 12 and a column address signal for specifying a column from which the reading operation is started is input to the column address buffer 13, a row address signal is supplied from the row address buffer 12 to the row decoder 14 in response to a /RAS signal and a readout starting column address signal is supplied from the column address buffer 13 to the column address counter 15 in response to a /CAS signal. As a result, one of the word lines is selected and driven by the row decoder 14, and at the same time, the readout starting column address signal is decoded by the column decoder 17 to control the column selection gate 16 and one of the bit lines is selected and charged. Data read out from a memory cell connected to the selected word line and bit line is supplied to the sense amplifier 18 via the column selection gate 16 and amplified and output to the data bus DB from the output buffer 19 in response to an /OE signal.
The column address counter 15 sequentially increments the content thereof one at a time in response to the /CAS signal to create a column address signal and supplies the same to the column decoder 17. As a result, memory data items are sequentially read out from the memory cells connected to the selected word line in the memory cell array 11.
After this, the word lines are sequentially selected, and the same readout operation is effected to read out data stored in the memory cell array 11.
However, with the above construction, there occurs a problem that data stored in the memory cell array 11 can be easily read out by sequentially incrementing the address of the ROM by use of a ROM writer or personal computer and the memory data can be easily copied by writing the readout data into a storage medium such as a hard disk or floppy disk.